It typically requires the most power and the largest physical footprint relative to the available bandwidth. Many modern ADCs support all three architectures. This is the art of frequency planning and involves a balance of available components and practical filter design. This leads to the concept of ADC sensitivity loss. The signal is further aliased to the 1 st Nyquist zone for processing. The receiver section of the recently released AD is a direct-conversion receiver and shown in Figure 2—note the similarity to Figure 1c.
the receiver sensitivity, as well as performance in a blocking condition.
Since the RF-sampling ADC replaces the signal chain from the mixer. Receiver Sensitivity Equation for Spread Spectrum Systems .
(ADC) in a sampling or sub-sampling receiver design, an RF designer needs to know the ADC's. Dynamic Performance Requirements for High-Performance ADCs and RF . receiver, sensitivity, dcma, multi-carrier, ADC, small-signal noise floor, SSNF.
Figure 3 shows the folding of the ADC input frequency and the first two harmonics as a function of input frequency relative to the Nyquist band frequencies. Henderson, Bert.
WJ Tech-Note, The obstacles have been operating the converters at speeds commensurate with direct RF sampling and achieving large input bandwidth. Table 1 compares the heterodyne, direct sampling, and direct-conversion architectures.
A Review of Wideband RF Receiver Architecture Options Analog Devices
Figure 1: One RF-sampling analog-to-digital converter (ADC) can reduces the impact of the ADC noise figure to the receiver sensitivity.
The basic topology is shown along with some of the benefits and challenges of each architecture. Direct Sampling. No mixing Practical at L-,S-band. Figure 1b shows a direct sampling receiver example. New York, Noble Publishing, SWaP Many Filters.
Maximum ADC bandwidth Simplest wideband option.
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|The signal is further aliased to the 1 st Nyquist zone for processing. It is also common to add an additional mixing stage to lower the frequency where very high dynamic range ADCs are available.
To minimize this degradation, the receiver noise is desired to be well above the ADC noise.
By mating the dual ADC with a quadrature demodulator, Channel 1 samples the I in phase signal and Channel 2 samples the Q quadrature signal.
In this architecture, all the receiver gain is at the operating band frequency, so careful layout is required if large receiver gain is desired. Architecture Comparison Table 1 compares the heterodyne, direct sampling, and direct-conversion architectures.